International On-Line Testing Symposium, 10th IEEE (IOLTS'04) Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection Funchal, Madeira Island, Portugal July 12-July 14 ISBN: 0-7695-2180-0
This paper presents an experimental evaluation of the effectiveness of the Master/Checker (M/C) architecture in a 32-bit Pentium processor system using both power-supply disturbance (PSD) fault injection and software-implemented fault injection (SWIFI) methods. A total of 6000 faults were injected inthe Master processor to measure the error detection coverage of the Checker processor. The results of the experiments with PSD fault injection show that the error detection coverage of the M/C architecture is about 66.13%, which is not quite effective. This low coverage depends on the high rate of Master processor hangs because of voltage fluctuation. The coverage increased to about 99.73% when an external watchdog was combined with the M/C architecture. In the case of SWIFI, the results show that the M/C architecture has reasonable outcome and is capable of detecting about100% of the errors.
Citation:
Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour, "Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection," iolts, pp.239, International On-Line Testing Symposium, 10th IEEE (IOLTS'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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