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International On-Line Testing Symposium, 10th IEEE (IOLTS'04)
A BIST-based Charge Analysis for Embedded Memories
Funchal, Madeira Island, Portugal
July 12-July 14
ISBN: 0-7695-2180-0
ASCII Text
x 
 
B. Alorda, V. Canals, I. de Pa?, J. Segura, "A BIST-based Charge Analysis for Embedded Memories," On-Line Testing Symposium, IEEE International, pp. 199, International On-Line Testing Symposium, 10th IEEE (IOLTS'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/OLT.2004.1319688,
author = {B. Alorda and V. Canals and I. de Pa? and J. Segura},
title = {A BIST-based Charge Analysis for Embedded Memories},
journal ={On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2004},
isbn = {0-7695-2180-0},
pages = {199},
doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2004.1319688},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - On-Line Testing Symposium, IEEE International
TI - A BIST-based Charge Analysis for Embedded Memories
SN - 0-7695-2180-0
SP
EP
A1 - B. Alorda,
A1 - V. Canals,
A1 - I. de Pa?,
A1 - J. Segura,
PY - 2004
KW - Current based testing
KW - charge based testing
KW - Embedded memories test
KW - built-in current monitors
VL - 0
JA - On-Line Testing Symposium, IEEE International
ER -
 
B. Alorda, Univ. de les Illes Balears
V. Canals, Univ. de les Illes Balears
I. de Pa?, Univ. de les Illes Balears
J. Segura, Univ. de les Illes Balears
We present a BIST architecture to perform Charge Based Analysis on embedded memories. The architecture includes a charge monitor as well as the input generation and output processing circuitry. The method applies a charge correlation technique validated experimentally on previous works for submicron SRAMs. The technique requires a short pre-characterization phase during manufacturing testing that guarantees process-variation immunity. The embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the BIST-charge analysis.
Index Terms:
Current based testing, charge based testing, Embedded memories test, built-in current monitors
Citation:
B. Alorda, V. Canals, I. de Pa?, J. Segura, "A BIST-based Charge Analysis for Embedded Memories," iolts, pp.199, International On-Line Testing Symposium, 10th IEEE (IOLTS'04), 2004
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