BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

I
IOLTS
2004
International On-Line Testing Symposium, 10th IEEE (IOLTS'04)
Abstract - BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

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	Similar Articles Articles by Patrick Girard Articles by Olivier H?ron Articles by Serge Pravossoudovitch Articles by Michel Renovell

International On-Line Testing Symposium, 10th IEEE (IOLTS'04)

Funchal, Madeira Island, Portugal

July 12-July 14

ISBN: 0-7695-2180-0

	ASCII Text	x
	Patrick Girard, Olivier H?ron, Serge Pravossoudovitch, Michel Renovell, "BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs," On-Line Testing Symposium, IEEE International, pp. 187, International On-Line Testing Symposium, 10th IEEE (IOLTS'04), 2004.

	BibTex	x
	@article{ 10.1109/OLT.2004.1319686, author = {Patrick Girard and Olivier H?ron and Serge Pravossoudovitch and Michel Renovell}, title = {BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs}, journal ={On-Line Testing Symposium, IEEE International}, volume = {0}, year = {2004}, isbn = {0-7695-2180-0}, pages = {187}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2004.1319686}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Symposium, IEEE International TI - BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs SN - 0-7695-2180-0 SP EP A1 - Patrick Girard, A1 - Olivier H?ron, A1 - Serge Pravossoudovitch, A1 - Michel Renovell, PY - 2004 KW - null VL - 0 JA - On-Line Testing Symposium, IEEE International ER -

Patrick Girard, Universit? Montpellier II / CNRS, France

Olivier H?ron, Universit? Montpellier II / CNRS, France

Serge Pravossoudovitch, Universit? Montpellier II / CNRS, France

Michel Renovell, Universit? Montpellier II / CNRS, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2004.1319686

In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a Manufacturing-Oriented Test (MOT) context. Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. The test of all the delay faults can be done with a reduced test sequence and does not require expensive ATE. To illustrate its feasibility, this BIST approach has been implemented in a VIRTEX FPGA from XILINX Inc.

Citation:

Patrick Girard, Olivier H?ron, Serge Pravossoudovitch, Michel Renovell, "BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs," iolts, pp.187, International On-Line Testing Symposium, 10th IEEE (IOLTS'04), 2004

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