In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal performance penalty, small hardware overhead and the benefits of at-speed testing.
Citation:
D. G. Nikolos, D. Nikolos, H. T. Vergos, C. Efstathiou, "An Efficient BIST scheme for High-Speed Adders," iolts, pp.89, 9th IEEE International On-Line Testing Symposium, 2003