Adiabatic process in thermodynamics transfers energy across zero temperature difference. The adiabatic CMOS design style attempts to switch a transistor to transfer energy across its source and drain while the voltage difference is zero. We define an adiabatic micro-architecture that pushes instructions across zero IPC gradient. The IPC gradient can be zero across time: for the same stage IPC over time does not vary, or across space: adjacent pipeline stages have zero variance. The reason to consider adiabatic micro-architectures is that the energy for a given computation can be show to be minimum for an adiabatic micro-architecture. An adiabatic compiler, really a back-end, is defined to be a compiler to support an adiabatic micro-architecture achieve its goals. The miniimal support provided by an adiabatic compiler includes a static estimatio of program ILP. We add new passes to the MachineSUIF compiler, to flag instruction groups that can potentially walk through a superscalar pipeline as a group. Hence, these instruction groups offer a fairly robust model of superscalar micro-architecture ILP. A compile time scheduling analysis can also generate instruction slack values. The slack indicates the program region within which a instruction can be scheduled. We also present a dispatch stage dynamic scheduling algorithm that utilizes the compiler annotated slacks to reschedule instructions with the explicit objective of minimizing the dispatch stage IPC variance. In other words, the proposed dispatch stage is adiabatic. Preliminary experimental results demonstrate an average reduction of 4.16% in IPC variance over SPEC2000 benchmarks with the adiabatic compiler and micro-architecture. The preliminary evaluation also shows the average processor dispatch stage energy reduction of 3.9% over the same SPEC2000 benchmarks. We expect to add similar IPC smoothening control knobs at instruction fetch and issue stages as well in the future, which should result in a more significant energy reduction.