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IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4
Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses
Como, Italy
July 24-July 27
ISBN: 0-7695-0619-4
ASCII Text
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Yoondong Park, J.-S. Liaw, T.W. Berger, B.J. Sheu, "Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses," Neural Networks, IEEE - INNS - ENNS International Joint Conference on, vol. 4, pp. 4214, IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4, 2000.
 
 
BibTex
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@article{ 10.1109/IJCNN.2000.860775,
author = {Yoondong Park and J.-S. Liaw and T.W. Berger and B.J. Sheu},
title = {Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses},
journal ={Neural Networks, IEEE - INNS - ENNS International Joint Conference on},
volume = {4},
year = {2000},
issn = {1098-7576},
pages = {4214},
doi = {http://doi.ieeecomputersociety.org/10.1109/IJCNN.2000.860775},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Neural Networks, IEEE - INNS - ENNS International Joint Conference on
TI - Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses
SN - 1098-7576
SP
EP
A1 - Yoondong Park,
A1 - J.-S. Liaw,
A1 - T.W. Berger,
A1 - B.J. Sheu,
PY - 2000
VL - 4
JA - Neural Networks, IEEE - INNS - ENNS International Joint Conference on
ER -
 
Yoondong Park, University of Southern California
J.-S. Liaw, University of Southern California
T.W. Berger, University of Southern California
B.J. Sheu, Avant Corporation
Low-power low-voltage mixed-analog/digital-signal CMOS technology is used in implementing a novel dynamic-synapse neural network microchip. A basic building block for dynamic process is implemented with a variable current source, resistors, charging/discharging capacitances, and transmission gates. It was designed and simulated in 0.35mm technology. The dynamic synapse function is implemented with resistor-capacitor exponential circuits, analog summing circuit, voltage comparator with hysteresis, and digital logic block. A neural network system with six input neurons, two output neurons, and 18 synapse is designed. Each neuron and dynamic synapse has individual threshold and gain. The circuit was simulated with two different input pulses to evaluate feedback inhibitory pulses, each action potential, and EPSP (Excitatory Post Synaptic Potential) of each dynamic processing point. Simulation results show that this dynamic synapse can be used for advanced neural processing including speech recognition application.
Citation:
Yoondong Park, J.-S. Liaw, T.W. Berger, B.J. Sheu, "Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses," ijcnn, vol. 4, pp.4214, IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4, 2000
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