Reconfigurable hardware devices such as FPGAs 1 (field programmable gate arrays) are cheap, flexible, and they offer both digital hardware efficiency and simple software-like handling. Their main advantages for neural network implementations are: reprogrammable FPGAs allow prototyping, FPGAs may be used for embedded applications, and FPGA-based implementations may be mapped on to new improved FPGAs (whereas neuroprocessors rapidly become outdated). However, the 2D-topology of FPGAs does not allow handling the complex connection graphs of standard neural models. Moreover, FPGAs still implement a limited number of logic gates, whereas neural computations involve area-greedy operators. Usual solutions ([3, 7, 13, 5, 4, 2]) handle sequentialized computations with a FPGA used as a small neuroprocessor, or they implement very small low-precision neural networks without on-chip learning. Connectivity problems are not solved even by the use of several FPGAs with a bit-serial arithmetic ([6]), or by the use of small-area operators (stochastic bit-stream in [1, 14], or frequency-based in [11]).The work described in this paper aims at developing neural architectures that are easy to map on to FPGAs, thanks to a simplified topology and an original data exchange scheme, without significant loss of approximation capability. It has been achieved thanks to the definition of a set of neural models called Field Programmable Neural Arrays (FPNA, see [9]). FPNAs may lead to the definition of neural networks adapted to hardware topological constraints. Different such neural networks may be derived from a given FPNA. They are called Field Programmed Neural Networks (FPNN). They reconcile the high connection density of neural architectures with the need of a limited interconnection scheme in hardware implementations.This paper focuses on the definition and implementation of FPNN parallel computation. A global study of FPNAs and FPNNs may be found in [9], whereas the use of FPGAs for neural implementations is justified in [10]. Section 2 shortly defines the FPNA-FPNN concept. It introduces a parallel form of FPNN computation, for feedforward and recurrent FPNNs. Section 3 describes an FPGA-based modular implementation based on asynchronous blocks. Section 4 rapidly mentions a few results of FPNN applications.