IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 2 Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning Como, Italy July 24-July 27 ISBN: 0-7695-0619-4
This paper describes a new pulse mode hardware multilayer neural network (MNN) that uses floating-point number system for synapse weights. Combined with pulse mode operation, the floating-point operation is implemented without multiplier. Furthermore, back-propagation algorithm is included in the hardware to provide on-chip learning capability. The proposed MNN is implemented on field programmable gate array (FPGA) and various experiments are conducted to test the performance of the proposed system. The results of the experiments show that the proposed MNN architecture can be used for applications that require high precision in their calculation, and its good on-chip learning capability is demonstrated.
Citation:
Hiroomi Hikawa, "Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning," ijcnn, vol. 2, pp.2071, IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 2, 2000 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||