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2004 International Conference on Parallel Processing (ICPP'04)
Architectural Characterization of an XML-Centric Commercial Server Workload
Montreal, Quebec, Canada
August 15-August 18
ISBN: 0-7695-2197-5
Padma Apparao, Intel Corporation
Ravi Iyer, Intel Corporation
Ricardo Morin, Intel Corporation
Naren Nayak, Intel Corporation
Mahesh Bhat, Intel Corporation
David Halliwell, Morgan Stanley
William Steinberg, Morgan Stanley
As XML (Extensible Markup Language) rapidly emerges as the standard for information storage and communication, it becomes increasingly important to understand its architectural characteristics and performance implications. In this paper, our goal is to characterize a representative XML-based server in a managed runtime environment such as Java*. Based on detailed measurements on an Intel? XeonTM processor-based commercial server running a real-world XML-based server workload, we start by looking at symmetric multiprocessor (SMP) scaling characteristics and the benefits of Hyper-Threading Technology. Using performance monitoring events provided on the processor, we present an overview of the architectural characteristics (such as clocks per instruction (CPI), cache miss rates, memory/bus utilization, branch behavior and efficiency). Using profiling tools like Intel® VTune™ Performance Analyzer, we map these architectural/performance characteristics to the various components of application execution -- helping us identify hot spots and propose potential enhancements to code generation and application software. We believe that the information presented in this paper will be useful in understanding the XML processing characteristics and may serve as a useful first step to identifying potential hardware/software optimizations for improved future performance.
Citation:
Padma Apparao, Ravi Iyer, Ricardo Morin, Naren Nayak, Mahesh Bhat, David Halliwell, William Steinberg, "Architectural Characterization of an XML-Centric Commercial Server Workload," icpp, pp.292-300, 2004 International Conference on Parallel Processing (ICPP'04), 2004
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