A SINGLE-CHIP LOW-POWER MPEG-4 AUDIOVISUAL LSI USING EMBEDDED DRAM TECHNOLOGY

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2001 IEEE International Conference on Multimedia and Expo (ICME'01)

Tokyo, Japan

August 22-August 25

ISBN: 0-7695-1198-8

	ASCII Text	x
	Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Tohru Furuyama, "A SINGLE-CHIP LOW-POWER MPEG-4 AUDIOVISUAL LSI USING EMBEDDED DRAM TECHNOLOGY," Multimedia and Expo, IEEE International Conference on, pp. 58, 2001 IEEE International Conference on Multimedia and Expo (ICME'01), 2001.

	BibTex	x
	@article{ 10.1109/ICME.2001.1237697, author = {Masafumi Takahashi and Tsuyoshi Nishikawa and Hideho Arakida and Tohru Furuyama}, title = {A SINGLE-CHIP LOW-POWER MPEG-4 AUDIOVISUAL LSI USING EMBEDDED DRAM TECHNOLOGY}, journal ={Multimedia and Expo, IEEE International Conference on}, volume = {0}, year = {2001}, isbn = {0-7695-1198-8}, pages = {58}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICME.2001.1237697}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multimedia and Expo, IEEE International Conference on TI - A SINGLE-CHIP LOW-POWER MPEG-4 AUDIOVISUAL LSI USING EMBEDDED DRAM TECHNOLOGY SN - 0-7695-1198-8 SP EP A1 - Masafumi Takahashi, A1 - Tsuyoshi Nishikawa, A1 - Hideho Arakida, A1 - Tohru Furuyama, PY - 2001 KW - null VL - 0 JA - Multimedia and Expo, IEEE International Conference on ER -

Masafumi Takahashi, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan

Tsuyoshi Nishikawa, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan

Hideho Arakida, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan

Tohru Furuyama, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICME.2001.1237697

A single-chip MPEG-4 audiovisual LSI based on the proposed scalable multiprocessor architecture has been developed for IMT-2000 multimedia applications. The LSI consists of three 16-bit multimedia-extended RISC processors and dedicated hardware accelerators, so as to achieve both low power consumption and high cost-effectiveness. It handles the MPEG- 4 video SP@L1 codec with the QCIF image at 15 frames per second, the AMR speech codec, and the ITU-T H.223 multiplexing at 60MHz consuming only 80mW, which is 33% of the previous design. The MPEG-4 audiovisual LSI was fabricated in 0.18us CMOS technology with quad metal using the embedded DRAM.

Citation:

Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Tohru Furuyama, "A SINGLE-CHIP LOW-POWER MPEG-4 AUDIOVISUAL LSI USING EMBEDDED DRAM TECHNOLOGY," icme, pp.58, 2001 IEEE International Conference on Multimedia and Expo (ICME'01), 2001

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