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2004 IEEE International Conference on Computer Design (ICCD'04)
A Minimal Dual-Core Speculative Multi-Threading Architecture
San Jose, CA
October 11-October 13
ISBN: 0-7695-2231-9
Srikanth T. Srinivasan, Intel Corporation
Haitham Akkary, Intel Corporation
Tom Holman, Intel Corporation
Konrad Lai, Intel Corporation
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpMT model that uses only two thread contexts. The model achieves significant speedups for single-threaded applications using a low-overhead scheme for detecting and selectively recovering from data dependence violations, and a novel Wrong Path Predictor to reduce the number of speculative threads executing along the wrong path. We also study the interactions between three previously proposed SpMT thread spawning policies that can be implemented dynamically in hardware - Fork on Call, Loop Continuation and Run Ahead policies - and show it is beneficial to implement all three policies together in a processor. While the individual thread spawning policies show performance benefits of 14%, 5% and 4% respectively on our SpMT model over a base processor that does not exploit SpMT, combining all three policies shows an average performance gain of 20%. Finally, we identify the sources of SpMT benefits - on average, 58% of the performance benefits due to SpMT comes from cache prefetching, 33% from instruction reuse, and 9% from branch precomputation and show all three sources of SpMT benefits must be utilized to realize the full potential of SpMT.
Citation:
Srikanth T. Srinivasan, Haitham Akkary, Tom Holman, Konrad Lai, "A Minimal Dual-Core Speculative Multi-Threading Architecture," iccd, pp.360-367, 2004 IEEE International Conference on Computer Design (ICCD'04), 2004
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