In this paper, we propose a floorplan-aware complexity reduction methodology for digital filters. The proposed scheme integrates high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay. Physical information of floorplan is incorporated into architecture synthesis. By considering interconnects while synthesizing reduced-complexity filters, the layout-centric architecture achieves better performance in the evolving scaled technologies. In our experiments, we achieved 15% improvement in critical-path delay over conventional design methodology.