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2004 IEEE International Conference on Computer Design (ICCD'04)
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2
San Jose, CA
October 11-October 13
ISBN: 0-7695-2231-9
Grigorios Magklis, Intel Barcelona Research Center
Jos? Gonz?lez, Intel Barcelona Research Center
Antonio Gonz?lez, Intel Barcelona Research Center
In this paper we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and Globally Asynchronous Locally Synchronous (GALS) designs. We also present a mechanism for dynamically adapting the frequency and voltage of the frontend of the CMCD with the goal to optimize the energy-delay^2 product (ED2P). Our mechanism has minimal hardware cost, is entirely self-adjustable, does not depend on any thresholds, and achieves results close to optimal. We evaluate it on 16 SPEC 2000 applications and report 17.5% ED2P reduction on average (80% of the upper bound).
Citation:
Grigorios Magklis, Jos? Gonz?lez, Antonio Gonz?lez, "Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2," iccd, pp.250-255, 2004 IEEE International Conference on Computer Design (ICCD'04), 2004
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