With the dramatic increase in mask costs, multi-project wafers have became an attractive choice for low-volume chip fabrication. By using the same set of masks to fabricate a number of different chips, the mask-set cost is amortized among different chip providers, leading to significant cost reduction especially for chip prototyping. In this paper we present a new algorithm for reticle floorplanning with wafer yield guarantees. The previous approach of Kahng et al. [Multi-Project Reticle Floorplanning and Wafer Dicing] considers optimizing both the reticle area and the wafer yield, leading to suboptimal solutions with no yield bounds. By contrast, we consider the yield as a constraint and optimize the area accordingly. We characterize yield constraints and provide a mechanism through which yield can be incorporated into an optimal-area packer. The incorporation of yield constraints prunes large parts of the search space of the optimal-area packer, leading to runtime-efficient optimal-area floorplans with guaranteed yields. Empirical results demonstrate that our approach dominates previous results, i.e., we give floorplans that consume less area and have higher die yields. For the 10 benchmarks studied in [Multi-Project Reticle Floorplanning and Wafer Dicing], we achieve a yield improvement of 14% with an area reduction of 2%.