Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels

I
ICCD
2003
2003 IEEE International Conference on Computer Design (ICCD'03)
Abstract - Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Anand Selvarathinam Articles by Euncheol Kim Articles by Gwan Choi

2003 IEEE International Conference on Computer Design (ICCD'03)

San Jose, California

October 13-October 15

ISBN: 0-7695-2025-1

	ASCII Text	x
	Anand Selvarathinam, Euncheol Kim, Gwan Choi, "Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels," Computer Design, International Conference on, pp. 520, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003.

	BibTex	x
	@article{ 10.1109/ICCD.2003.1240949, author = {Anand Selvarathinam and Euncheol Kim and Gwan Choi}, title = {Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-6404}, pages = {520}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240949}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels SN - 1063-6404 SP EP A1 - Anand Selvarathinam, A1 - Euncheol Kim, A1 - Gwan Choi, PY - 2003 KW - LDPC Decoder KW - Serial Architecture KW - Parallel Architecture KW - Fibre Channel KW - VLSI KW - Hardware Scaling VL - 0 JA - Computer Design, International Conference on ER -

Anand Selvarathinam, Texas A&M University

Euncheol Kim, Texas A&M University

Gwan Choi, Texas A&M University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240949

A requirement-specific decoder design for forward error-correction in 2 Gbps optical fiber communication system is presented. Low-density parity-check codes are used to achieve high bit error rate performance. Several novel error- decoding architectures are proposed and their design configurations explored to identify optimal cost/performance design. Serial, parallel and scalable architectures are studied. The result is a scaleable architecture that consists of 1.3 million CMOS gates running at 295 Mhz and it achieves a throughput of 2.51 Gbps.

Index Terms:

LDPC Decoder, Serial Architecture, Parallel Architecture, Fibre Channel, VLSI, Hardware Scaling

Citation:

Anand Selvarathinam, Euncheol Kim, Gwan Choi, "Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels," iccd, pp.520, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.