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2003 IEEE International Conference on Computer Design (ICCD'03)
CMOS High-Speed I/Os - Present and Future
San Jose, California
October 13-October 15
ISBN: 0-7695-2025-1
ASCII Text
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M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John Edmondson, John Poulton, "CMOS High-Speed I/Os - Present and Future," Computer Design, International Conference on, pp. 454, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003.
 
 
BibTex
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@article{ 10.1109/ICCD.2003.1240940,
author = {M.-J. Edward Lee and William J. Dally and Ramin Farjad-Rad and Hiok-Tiaq Ng and Ramesh Senthinathan and John Edmondson and John Poulton},
title = {CMOS High-Speed I/Os - Present and Future},
journal ={Computer Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-6404},
pages = {454},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240940},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Design, International Conference on
TI - CMOS High-Speed I/Os - Present and Future
SN - 1063-6404
SP
EP
A1 - M.-J. Edward Lee,
A1 - William J. Dally,
A1 - Ramin Farjad-Rad,
A1 - Hiok-Tiaq Ng,
A1 - Ramesh Senthinathan,
A1 - John Edmondson,
A1 - John Poulton,
PY - 2003
KW - null
VL - 0
JA - Computer Design, International Conference on
ER -
 
M.-J. Edward Lee, Velio Communications, Inc.
William J. Dally, Stanford University; Velio Communications, Inc.
Ramin Farjad-Rad, Velio Communications, Inc.
Hiok-Tiaq Ng, Velio Communications, Inc.
Ramesh Senthinathan, Velio Communications, Inc.
John Edmondson, Velio Communications, Inc.
John Poulton, Velio Communications, Inc.
High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technology enables chips with over 1 Tb/s of I/O bandwidth today and over 10 Tb/s of bandwidth by 2010 as both signaling rates and number of high-speed I/Os increase with process scaling. Key technologies that enable this growth in I/O performance include low-jitter clock circuits and equalized signaling. An analysis of clock jitter and channel interference suggests that signaling rates should track transistor performance to rates of at least 40 Gb/s over boards, back-planes, and short-distance cables.
Citation:
M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John Edmondson, John Poulton, "CMOS High-Speed I/Os - Present and Future," iccd, pp.454, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003
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