2003 IEEE International Conference on Computer Design (ICCD'03) Optimal Inductance for On-chip RLC Interconnections San Jose, California October 13-October 15 ISBN: 0-7695-2025-1
We propose the concept of an optimal inductance value that can substantially reduce delay of global RLC signals while maintaining good signal integrity (low ringing/overshoot). We exploit the fact that inductance results in faster transition times to improve delay of buffers in global signal lines. We observe that voltage overshoot, slew rate, and total line delay all show strong inflection points at the same value of inductance. At this optimal value of inductance significant improvements in signal transition time, and hence in overall signal delay, are obtained with negligible ringing. We propose adjusting the power grid to achieve this optimal inductance. Results show that the delay of a 1cm line with 9 inserted repeaters can be reduced by 8-12% with acceptable ringing by operating at the optimal inductance point.
Citation:
Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester, "Optimal Inductance for On-chip RLC Interconnections," iccd, pp.264, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||