2003 IEEE International Conference on Computer Design (ICCD'03)
A Mixed-Mode Delay-Locked-Loop Architecture
San Jose, California
October 13-October 15
ISBN: 0-7695-2025-1
We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover, circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.
Citation:
Daniel Eckerbert, Lars "J." Svensson, Per Larsson-Edefors, "A Mixed-Mode Delay-Locked-Loop Architecture," iccd, pp.261, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003