Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor

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2003 IEEE International Conference on Computer Design (ICCD'03)

San Jose, California

October 13-October 15

ISBN: 0-7695-2025-1

	ASCII Text	x
	Joel Grodstein, Dilip Bhavsar, Vijay Bettada, Richard Davies, "Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor," Computer Design, International Conference on, pp. 180, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003.

	BibTex	x
	@article{ 10.1109/ICCD.2003.1240892, author = {Joel Grodstein and Dilip Bhavsar and Vijay Bettada and Richard Davies}, title = {Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-6404}, pages = {180}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240892}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor SN - 1063-6404 SP EP A1 - Joel Grodstein, A1 - Dilip Bhavsar, A1 - Vijay Bettada, A1 - Richard Davies, PY - 2003 KW - null VL - 0 JA - Computer Design, International Conference on ER -

Joel Grodstein, Intel Corporation, Shrewsbury, MA

Dilip Bhavsar, Intel Corporation, Shrewsbury, MA

Vijay Bettada, Intel Corporation, Shrewsbury, MA

Richard Davies, Intel Corporation, Shrewsbury, MA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240892

We present our experiences generating scan-based critical-path tests for the partial-scan Alpha 21364 microprocessor, including the effects of crosstalk and multiple-inputs switching on path delay. Insufficient scan penetration made this difficult[1], but a new ATPG algorithm increased our coverage. Comparison with actual silicon shows interesting results; we explain them with statistical analysis, factoring the effect of statistical process variation into the effects of crosstalk and multiple-input switching on delay. Finally, we draw conclusions about how to help make future designs amenable to speed testing.

Citation:

Joel Grodstein, Dilip Bhavsar, Vijay Bettada, Richard Davies, "Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor," iccd, pp.180, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003

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