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2003 IEEE International Conference on Computer Design (ICCD'03)
Low Power Adder with Adaptive Supply Voltage
San Jose, California
October 13-October 15
ISBN: 0-7695-2025-1
Hiroaki Suzuki, Purdue University, West Lafayette
Woopyo Jeong, Purdue University, West Lafayette
Kaushik Roy, Purdue University, West Lafayette
Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a low power adder, which adaptively selects supply voltages based on the input vector patterns. We prototyped a 32-bit Ripple Carry Adder and analyzed the power consumption and performance in details. Results show 29% improvement in power consumption over a conventional ripple carry adder with comparable performance.
Citation:
Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy, "Low Power Adder with Adaptive Supply Voltage," iccd, pp.103, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003
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