2002 IEEE International Conference on Computer Design (ICCD'02) Adaptive Pipeline Depth Control for Processor Power-Management Freiburg, Germany September 16-September 18 ISBN: 0-7695-1700-5
A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them ?permanently? transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.
Citation:
Aristides Efthymiou, Jim D. Garside, "Adaptive Pipeline Depth Control for Processor Power-Management," iccd, pp.454, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||