2002 IEEE International Conference on Computer Design (ICCD'02) Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques Freiburg, Germany September 16-September 18 ISBN: 0-7695-1700-5
Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circuit characteristics to define the concept of resistance-dominant and inductance-dominant lines. This notion is used to progressively refine a set of clusters that are inductively tightly-coupled. For reasonable designs, the more exact Algorithm 1 yields a sparsification of 97% for delay and oscillation magnitude errors of 10% and 15%, respectively, while the more approximate Algorithm 2 achieves up to 99% sparsification. An offshoot of this work is K-PRIMA, an extension of PRIMA to handle K matrices with guaranteed passivity.
Citation:
Haitian Hu, Sachin S. Sapatnekar, "Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques," iccd, pp.434, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||