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2002 IEEE International Conference on Computer Design (ICCD'02)
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Freiburg, Germany
September 16-September 18
ISBN: 0-7695-1700-5
D. Duarte, Intel Corporation
N. Vijaykrishnan, Pennsylvania State University
M.J. Irwin, Pennsylvania State University
H-S Kim, Pennsylvania State University
G. McFarland, Intel Corporation
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, circuit design and micro-architectural changes are required. Consequently, to focus the optimization efforts in the right direction, the models proposed and studies performed in this work are a first step for understanding the relative importance of leakage and dynamic energy in future technologies. Further, we analyze the effectiveness of two energy reduction mechanisms that employ voltage scaling, namely, supply and threshold voltage selection. We consider the impact of imminent technology changes and packaging improvements while showing that neglecting the impact of temperature may lead to underestimate the power savings by up to 19.5%.
Citation:
D. Duarte, N. Vijaykrishnan, M.J. Irwin, H-S Kim, G. McFarland, "Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes," iccd, pp.382, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
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