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2002 IEEE International Conference on Computer Design (ICCD'02)
k-time Forced Simulation: A Formal Verification Technique for IP Reuse
Freiburg, Germany
September 16-September 18
ISBN: 0-7695-1700-5
Partha S. Roop, University of Auckland
A. Sowmya, University of New South Wales
S. Ramesh, Indian Institute of Technology at Bombay
Automatic IP (Intellectual Property) matching is a key to reuse of IP cores. This paper presents an IP matching algorithm that can check whether a given programmable IP block can be adapted to match a given specificatio n. When such adaptation is possible, the algorithm also generates a device driver to adapt the IP block. Though simulation, refinement and bisimulation based algorithms exist, they cannot be used to check the adaptability of an IP block, which is the essence of reuse. The IP matching algorithm is based on a formal verification technique called k-time forced simulation proposed in this paper. k-time forced simulation may be used for identifying whether a given IP block (a device D can be adapted to match a specification (a function F), given that D has a clock that is k-times faster than F. We demonstrate the applicability of the algorithm by reusing several IP Blocks.
Citation:
Partha S. Roop, A. Sowmya, S. Ramesh, "k-time Forced Simulation: A Formal Verification Technique for IP Reuse," iccd, pp.50, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002
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