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1999 IEEE International Conference on Computer Design (ICCD'99)
Synthesis of Arrays and Records
Austin, Texas
October 10-October 13
ISBN: 0-7695-0406-X
Pradip K. Jha, IBM EDA Lab
Steven Barnfield, IBM EDA Lab
John Weaver, IBM EDA Lab
Rudra Mukherjee, ViewLogic Systems Incorporated
Reinaldo A. Bergamaschi, IBM T. J. Watson Research Center
The use of arrays and records in modern hardware-description languages (HDL) allows designs to be modeled at very high levels of abstraction. However, the support for these complex data types in current synthesis tools is very limited. This paper presents a comprehensive scheme to synthesize aggregate data types such as arrays and records, in a very general manner. The approach consists of mapping objects (variables and signals) of aggregate data types onto one-dimensional vectors, and generating specialized addressing/decoding hardware to be able to access any field of the data type. Arrays of multiple dimensions and any level of nesting of arrays and records are supported. This paper describes the whole process, from the language specification to the actual hardware structures created by synthesis.
Index Terms:
Aggregate data types, Array, Record, Synthesis
Citation:
Pradip K. Jha, Steven Barnfield, John Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi, "Synthesis of Arrays and Records," iccd, pp.614, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999
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