SOI Implementation of a 64-Bit Adder

I
ICCD
1999
1999 IEEE International Conference on Computer Design (ICCD'99)
Abstract - SOI Implementation of a 64-Bit Adder

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	Similar Articles Articles by J.V. Tran Articles by F. Mounes-Toussi Articles by S.N. Storino Articles by D.L. Stasiak

1999 IEEE International Conference on Computer Design (ICCD'99)

Austin, Texas

October 10-October 13

ISBN: 0-7695-0406-X

	ASCII Text	x
	J.V. Tran, F. Mounes-Toussi, S.N. Storino, D.L. Stasiak, "SOI Implementation of a 64-Bit Adder," Computer Design, International Conference on, pp. 573, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.

	BibTex	x
	@article{ 10.1109/ICCD.1999.808598, author = {J.V. Tran and F. Mounes-Toussi and S.N. Storino and D.L. Stasiak}, title = {SOI Implementation of a 64-Bit Adder}, journal ={Computer Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-6404}, pages = {573}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808598}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - SOI Implementation of a 64-Bit Adder SN - 1063-6404 SP EP A1 - J.V. Tran, A1 - F. Mounes-Toussi, A1 - S.N. Storino, A1 - D.L. Stasiak, PY - 1999 VL - 0 JA - Computer Design, International Conference on ER -

J.V. Tran, IBM Corporation

F. Mounes-Toussi, IBM Corporation

S.N. Storino, IBM Corporation

D.L. Stasiak, IBM Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808598

Silicon{On{Insulator (SOI) technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel effect, and soft error immunity. However, the floating body effect in SOI devices and the resulting hysteresis poses major challenges for dynamic circuit designers. In this paper, we describe implementation of a 64-bit adder and some of the techniques used to overcome the parasitic bipolar discharge effect while maintaining performance.

Citation:

J.V. Tran, F. Mounes-Toussi, S.N. Storino, D.L. Stasiak, "SOI Implementation of a 64-Bit Adder," iccd, pp.573, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999

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