1999 IEEE International Conference on Computer Design (ICCD'99) Design for Testability to Combat Delay Faults Austin, Texas October 10-October 13 ISBN: 0-7695-0406-X
To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverage, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips.
Index Terms:
LSSD, SRL, BIST, LFSR, MISR, Delay Test
Citation:
Jacob Savir, "Design for Testability to Combat Delay Faults," iccd, pp.407, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||