Design for Testability to Combat Delay Faults

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1999 IEEE International Conference on Computer Design (ICCD'99)

Austin, Texas

October 10-October 13

ISBN: 0-7695-0406-X

	ASCII Text	x
	Jacob Savir, "Design for Testability to Combat Delay Faults," Computer Design, International Conference on, pp. 407, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.

	BibTex	x
	@article{ 10.1109/ICCD.1999.808574, author = {Jacob Savir}, title = {Design for Testability to Combat Delay Faults}, journal ={Computer Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-6404}, pages = {407}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808574}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Design for Testability to Combat Delay Faults SN - 1063-6404 SP EP A1 - Jacob Savir, PY - 1999 KW - LSSD KW - SRL KW - BIST KW - LFSR KW - MISR KW - Delay Test VL - 0 JA - Computer Design, International Conference on ER -

Jacob Savir, New Jersey Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808574

To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverage, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips.

Index Terms:

LSSD, SRL, BIST, LFSR, MISR, Delay Test

Citation:

Jacob Savir, "Design for Testability to Combat Delay Faults," iccd, pp.407, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999

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