A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology

I
ICCD
1999
1999 IEEE International Conference on Computer Design (ICCD'99)
Abstract - A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology

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1999 IEEE International Conference on Computer Design (ICCD'99)

Austin, Texas

October 10-October 13

ISBN: 0-7695-0406-X

	ASCII Text	x
	Avinask K. Gautam, Jagadish Rao, Karthikeyan Madathil, Vilesh Shah, H Udayakumar, Amitabh Menon, Subash Chandar, "A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology," Computer Design, International Conference on, pp. 340, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.

	BibTex	x
	@article{ 10.1109/ICCD.1999.808564, author = {Avinask K. Gautam and Jagadish Rao and Karthikeyan Madathil and Vilesh Shah and H Udayakumar and Amitabh Menon and Subash Chandar}, title = {A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology}, journal ={Computer Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-6404}, pages = {340}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808564}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology SN - 1063-6404 SP EP A1 - Avinask K. Gautam, A1 - Jagadish Rao, A1 - Karthikeyan Madathil, A1 - Vilesh Shah, A1 - H Udayakumar, A1 - Amitabh Menon, A1 - Subash Chandar, PY - 1999 KW - Design Methodology KW - Synthesis KW - Links to layout KW - Deep sub-micron KW - Physical Design KW - DSP VL - 0 JA - Computer Design, International Conference on ER -

Avinask K. Gautam, Texas Instruments India Ltd

Jagadish Rao, Texas Instruments India Ltd

Karthikeyan Madathil, Texas Instruments India Ltd

Vilesh Shah, Texas Instruments India Ltd

H Udayakumar, Texas Instruments India Ltd

Amitabh Menon, Texas Instruments India Ltd

Subash Chandar, Texas Instruments India Ltd

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808564

We present a design methodology that was used to design a 150MHz DSP core in a deep sub-micron technology, with emphasis on high speed and fast design cycle time. We detail the methodology, primarily based on synthesis, describe how we coupled synthesis to placement and layout and present data on our timing convergence results. We present data on experiments that we performed to tune specific steps of the methodology, which were critical to make the methodology successful.

Index Terms:

Design Methodology, Synthesis, Links to layout, Deep sub-micron, Physical Design, DSP

Citation:

Avinask K. Gautam, Jagadish Rao, Karthikeyan Madathil, Vilesh Shah, H Udayakumar, Amitabh Menon, Subash Chandar, "A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology," iccd, pp.340, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999

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