Although tree multipliers result in good logic depth, they are not amenable to dense VLSI implementation due to the complexity of wiring. We have addressed the issue of optimal partial product reduction for parallel tree multipliers. An algorithm has been developed to trade-off wiring complexity with logic depth. An automatic generator has been developed to generate netlist for any size multiplier with optimized placement information. This netlist with placement information is taken through a data-path place and route tool to create compact layout for the generated multipliers. The results indicate that the performance of the generated multipliers in terms of speed can be similar to custom designed multipliers.