1999 IEEE International Conference on Computer Design (ICCD'99) Performance Driven Optimization of Network Length in Physical Placement Austin, Texas October 10-October 13 ISBN: 0-7695-0406-X
A novel technique to significantly improve the performance of a design by the movement of sets of gates during or after timing driven placement is proposed. A method to identify optimal set of circuit(gate) movements to enhance timing is presented. Experimental results with a min-cut placement tool indicate that the proposed approach of direct manipulation of circuit locations, significantly improves the timing of large partitions of a chip.
Citation:
Wilm Donath, Prabhakar Kudva, Lakshmi Reddy, "Performance Driven Optimization of Network Length in Physical Placement," iccd, pp.258, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||