Evaluation of Computing in Memory Architectures for Digital Image Processing Applications

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1999 IEEE International Conference on Computer Design (ICCD'99)

Austin, Texas

October 10-October 13

ISBN: 0-7695-0406-X

	ASCII Text	x
	David Landis, Paul Hulina, Scott Deno, Luke Roth, Lee Coraor, "Evaluation of Computing in Memory Architectures for Digital Image Processing Applications," Computer Design, International Conference on, pp. 146, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.

	BibTex	x
	@article{ 10.1109/ICCD.1999.808419, author = {David Landis and Paul Hulina and Scott Deno and Luke Roth and Lee Coraor}, title = {Evaluation of Computing in Memory Architectures for Digital Image Processing Applications}, journal ={Computer Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-6404}, pages = {146}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808419}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Evaluation of Computing in Memory Architectures for Digital Image Processing Applications SN - 1063-6404 SP EP A1 - David Landis, A1 - Paul Hulina, A1 - Scott Deno, A1 - Luke Roth, A1 - Lee Coraor, PY - 1999 KW - Computing In Memory KW - System-On-A-Chip KW - Parallel Processing KW - Image Processing KW - Multiprocessor KW - FPGA KW - DRAM VL - 0 JA - Computer Design, International Conference on ER -

David Landis, Pennsylvania State University

Paul Hulina, Pennsylvania State University

Scott Deno, Pennsylvania State University

Luke Roth, Pennsylvania State University

Lee Coraor, Pennsylvania State University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808419

Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these architectures can be custom tailored to the demands of real-time image processing. This paper identifies and describes candidate computing in memory architectures, and evaluates their performance on several image-processing algorithms.

Index Terms:

Computing In Memory, System-On-A-Chip, Parallel Processing, Image Processing, Multiprocessor, FPGA, DRAM

Citation:

David Landis, Paul Hulina, Scott Deno, Luke Roth, Lee Coraor, "Evaluation of Computing in Memory Architectures for Digital Image Processing Applications," iccd, pp.146, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999

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