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1999 IEEE International Conference on Computer Design (ICCD'99)
Designing the M?CORE™ M3 CPU Architecture
Austin, Texas
October 10-October 13
ISBN: 0-7695-0406-X
ASCII Text
x 
 
Jeff Scott, Lea Hwang Lee, Ann Chin, John Arends, Bill Moyer, "Designing the M?CORE™ M3 CPU Architecture," Computer Design, International Conference on, pp. 94, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.
 
 
BibTex
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@article{ 10.1109/ICCD.1999.808407,
author = {Jeff Scott and Lea Hwang Lee and Ann Chin and John Arends and Bill Moyer},
title = {Designing the M?CORE™ M3 CPU Architecture},
journal ={Computer Design, International Conference on},
volume = {0},
year = {1999},
issn = {1063-6404},
pages = {94},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808407},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Design, International Conference on
TI - Designing the M?CORE™ M3 CPU Architecture
SN - 1063-6404
SP
EP
A1 - Jeff Scott,
A1 - Lea Hwang Lee,
A1 - Ann Chin,
A1 - John Arends,
A1 - Bill Moyer,
PY - 1999
KW - Low-power
KW - high-performance
KW - embedded applications
KW - embedded processor core
VL - 0
JA - Computer Design, International Conference on
ER -
 
Jeff Scott, Motorola Incorporated
Lea Hwang Lee, Motorola Incorporated
Ann Chin, Motorola Incorporated
John Arends, Motorola Incorporated
Bill Moyer, Motorola Incorporated
The MCORE microRISC architecture has been developed to address the growing need for long battery life among today's portable applications. In this paper, we present the architectural enhancements of the M3 processor, the successor to the original MCORE M2 architecture. Specifically, we discuss the instruction buffer and pipeline enhancements, the branch prediction algorithm, branch folding for small program loops, the fast integer multiplier, and several new instructions. We present performance comparisons between the M2 and M3 MCORE processors. Finally, we also discuss two system implementations utilizing the MCORE M3 processor.
Index Terms:
Low-power, high-performance, embedded applications, embedded processor core
Citation:
Jeff Scott, Lea Hwang Lee, Ann Chin, John Arends, Bill Moyer, "Designing the M?CORE™ M3 CPU Architecture," iccd, pp.94, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999
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