Given a pseudo-synchronous (sampled input) finite-state machine implementation of a real-time controller (e.g., RTL Verilog code), and a timing diagrams (TDs) specification, the question we wish to answer is whether the controller satisfies this specification. Our method uses Constraint Logic Programming (CLP). The controller FSM is fed with input sequences derived from the assumption constraints on the inputs as stated in the TD, and its outputs are verified against the required timing (commit) constraints in the TD. Our technique considers all input sequences in one consistency check for each commit constraint, carried out on a system of constraints constructed from the TD and the unfolded controller FSM. The number of constraints is linear in the lengths of the intervals of the assumption constraints. The method was implemented in CLP (BNR) Prolog which is based on relational interval arithmetic (RIA). We verified a controller for an asynchronous bus.