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1998 IEEE International Conference on Computer Design (ICCD'98)
Design Methodology for a 1.0 GHz Microprocessor
Austin, Texas
October 05-October 05
ISBN: 0-8186-9099-2
ASCII Text
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S. Posluszny, N. Aoki, D. Boerstler, J. Burns, S. Dhong, U. Ghoshal, P. Hofstee, D. LaPotin, K. Lee, D. Meltzer, H. Ngo, K. Nowka, J. Silberman, O. Takahashi, I. Vo, "Design Methodology for a 1.0 GHz Microprocessor," Computer Design, International Conference on, pp. 17, 1998 IEEE International Conference on Computer Design (ICCD'98), 1998.
 
 
BibTex
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@article{ 10.1109/ICCD.1998.727018,
author = {S. Posluszny and N. Aoki and D. Boerstler and J. Burns and S. Dhong and U. Ghoshal and P. Hofstee and D. LaPotin and K. Lee and D. Meltzer and H. Ngo and K. Nowka and J. Silberman and O. Takahashi and I. Vo},
title = {Design Methodology for a 1.0 GHz Microprocessor},
journal ={Computer Design, International Conference on},
volume = {0},
year = {1998},
issn = {1063-6404},
pages = {17},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1998.727018},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Design, International Conference on
TI - Design Methodology for a 1.0 GHz Microprocessor
SN - 1063-6404
SP
EP
A1 - S. Posluszny,
A1 - N. Aoki,
A1 - D. Boerstler,
A1 - J. Burns,
A1 - S. Dhong,
A1 - U. Ghoshal,
A1 - P. Hofstee,
A1 - D. LaPotin,
A1 - K. Lee,
A1 - D. Meltzer,
A1 - H. Ngo,
A1 - K. Nowka,
A1 - J. Silberman,
A1 - O. Takahashi,
A1 - I. Vo,
PY - 1998
KW - design
KW - microprocessor
KW - methodology
KW - powerpc
KW - dynamic
KW - circuit
KW - microarchitecture
KW - tools
KW - timing
KW - VHDL
KW - DCL
VL - 0
JA - Computer Design, International Conference on
ER -
 
N. Aoki, IBM
J. Burns, IBM
S. Dhong, IBM
K. Lee, IBM
H. Ngo, IBM
K. Nowka, IBM
I. Vo, IBM
This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM's Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.
Index Terms:
design, microprocessor, methodology, powerpc, dynamic, circuit, microarchitecture, tools, timing, VHDL, DCL
Citation:
S. Posluszny, N. Aoki, D. Boerstler, J. Burns, S. Dhong, U. Ghoshal, P. Hofstee, D. LaPotin, K. Lee, D. Meltzer, H. Ngo, K. Nowka, J. Silberman, O. Takahashi, I. Vo, "Design Methodology for a 1.0 GHz Microprocessor," iccd, pp.17, 1998 IEEE International Conference on Computer Design (ICCD'98), 1998
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