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10th International Symposium on High Performance Computer Architecture (HPCA'04)
Reducing Branch Misprediction Penalty via Selective Branch Recovery
Madrid, Spain
February 14-February 18
ISBN: 0-7695-2053-7
Amit Gandhi, Intel Corporation and Portland State University
Haitham Akkary, Intel Corporation and Portland State University
Srikanth T. Srinivasan, Intel Corporation

Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipeline with useful instructions once the branch is resolved. Current processor trends, large instruction windows and deep pipelines, amplify both components of the branch misprediction penalty.

In this paper, we propose a novel method, called Selective Branch Recovery (SBR), to reduce both components of branch misprediction penalty. SBR exploits a frequently occurring type of control independence — exact convergence — where the mispredicted path converges exactly at the beginning of the correct path. In such cases, SBR selectively reuses the results computed during mis-speculative execution and obviates the need to fetch or rename convergent instructions again. Thus, SBR addresses both components of branch misprediction penalty. To increase the likelihood of branch mispredictions that can be handled with SBR, we also present an effective means for inducing exact convergence on mis-speculative paths. With SBR, we significantly improve performance (between 3%-22%, average 8%) on a wide range of benchmarks over our baseline processor that does not exploit SBR.

Citation:
Amit Gandhi, Haitham Akkary, Srikanth T. Srinivasan, "Reducing Branch Misprediction Penalty via Selective Branch Recovery," hpca, pp.254, 10th International Symposium on High Performance Computer Architecture (HPCA'04), 2004
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