Conventional address translation mechanisms generally use a translation look aside buffer cache (TLB) of current page translations to provide virtual to physical page addressing. This translation cache is generally shared amongst all processes, and between reference types irrespective as to whether they relate to instruction or data references. In this paper we introduce a reconfigurable partitioned TLB which improves TLB performance by removing cache conflict misses between the distinct reference types. Extensive simulations using selected SPEC95 workloads show that data reference translations unfairly compete with instruction reference translations by dominating a standard shared TLB. We compare the traditional shared TLB with both fixed partition and re-configurable fixed partition TLB structures that segregate instruction and data page translation entries. We show that the partitioned TLB operates optimally when the miss ratio of the instruction reference partition is maintained at a lower level than the miss ratio for the data reference partition. By dynamically preserving a balance between the translation performance of instruction and data components, a protected `working set' of instruction translation entries can be maintained. This can be achieved within the one TLB structure with soft partitions separating reference types.