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28th Hawaii International Conference on System Sciences (HICSS'95)
Hawaii, USA
January 04-January 07
ISBN: 0-8186-6935-7
T. Yamada, Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
K. Yamamoto, Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
S. Ueno, Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Motivated by the design of fault-tolerant multiprocessor interconnection networks the paper considers the following problem: given a positive integer t and graph H, construct a graph G from H by adding a minimum number /spl Delta/(t,H) of edges such that even after deleting any t edges from G the remaining graph contains H as a subgraph. We estimate /spl Delta/(t,H) for the hypercube and torus, which are well-known as important interconnection networks for multiprocessor systems. If we denote the hypercube and square torus on N vertices by Q/sub N/ and D/sub N/, respectively, we show among others, that /spl Delta/(t,Q/sub N/)=O(tNlog(logN/t+log2e)) for any t and N (t/spl ges/2), and /spl Delta/(1,D/sub N/)=N/2 if N is even.
Index Terms:
hypercube networks; multiprocessor interconnection networks; fault tolerant computing; graph theory; fault-tolerant graphs; fault-tolerant multiprocessor interconnection networks; hypercubes; tori; subgraph
Citation:
T. Yamada, K. Yamamoto, S. Ueno, "Fault-tolerant graphs for hypercubes and tori," hicss, pp.499, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995
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