Sangho Ha, Dept. of Comput. Sci. & Stat., Seoul Nat. Univ., South Korea
Sangyong Han, Dept. of Comput. Sci. & Stat., Seoul Nat. Univ., South Korea
Heunghwan Kim, Dept. of Comput. Sci. & Stat., Seoul Nat. Univ., South Korea
Multithreading is attractive in a large-scale parallel system since it allows split-phase memory operations and fast context switching between computations without blocking the processor. The performance of multithreaded architectures depends significantly on the quality of multithreaded codes. In this paper, we describe an enhanced thread formation scheme to produce efficient sequential threads from programs written in Id/sup -/, a lenient parallel language. This scheme features graph partitioning based only on long latency instructions, a combination of multiple switches and merges introducing a generalized switch-and-merge, thread merging, and redundant arc elimination using thread precedence relations. Simulation results show that our scheme reduces control and branch instructions effectively.
Index Terms:
parallel languages; merging; large-scale systems; switching; program control structures; graph theory; parallel architectures; lenient parallel language; language partitioning; sequential threads; multithreaded architecture performance; large-scale parallel system; split-phase memory operations; fast context switching; multithreaded code quality; enhanced thread formation scheme; Id/sup -/; graph partitioning; long latency instructions; multiple switches; generalized switch-and-merge; thread merging; redundant arc elimination; thread precedence relations; simulation; control instructions; branch instructions; DAVRID multithreaded architecture
Citation:
Sangho Ha, Sangyong Han, Heunghwan Kim, "Partitioning a lenient parallel language into sequential threads," hicss, pp.83, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995
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