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28th Hawaii International Conference on System Sciences (HICSS'95)
Hawaii, USA
January 04-January 07
ISBN: 0-8186-6930-6
T.D. Burd, California Univ., Berkeley, CA, USA
R.W. Brodersen, California Univ., Berkeley, CA, USA
Reduction of power dissipation in microprocessor design is becoming a key design constraint. This is motivated not only by portable electronics, in which battery weight and size is critical, but by heat dissipation issues in larger desktop and parallel machines as well. By identifying the major modes of computation of these processors and by proposing figures of merit for each of these modes, a power analysis methodology is developed. It allows the energy efficiency of various architectures to be quantified, and provides techniques for either individually optimizing or trading off throughput and energy consumption. The methodology is then used to qualify three important design principles for energy-efficient microprocessor design.
Index Terms:
CMOS digital integrated circuits; microprocessor chips; cooling; energy conservation; computer architecture; integrated circuit modelling; energy efficient CMOS microprocessor design; power dissipation; portable electronics; battery weight; battery size; heat dissipation; desktop computers; parallel machines; computation modes; figures of merit; power analysis methodology; energy efficiency quantification; computer architectures; throughput; energy consumption; design principles
Citation:
T.D. Burd, R.W. Brodersen, "Energy efficient CMOS microprocessor design," hicss, pp.288, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995
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