To avoid RISC processors accessing the external memory, an increased number of processor registers is desirable. However, sophisticated concepts are needed for the handling of large amounts of registers. Multi Windows are an improved version of Threaded Windows, the first dynamic register array concept. Both utilize dynamic register allocation for handling a very large number of general purpose registers. This concept enables fast context switches and a short interrupt latency, which makes it suitable for real time systems. In Multi Windows, the data structures were simplified and improved. Exception routines are less complex and faster. Both concepts are discussed in this article.
Index Terms:
reduced instruction set computing; data structures; storage allocation; interrupts; dynamic register array concept; high-performance RISC processors; external memory; processor registers; registers; Multi Windows; Threaded Windows; dynamic register array; dynamic register allocation; general purpose registers; fast context switches; short interrupt latency; real time systems; data structures; exception routines
Citation:
T. Scholz, M. Schafers, "An improved dynamic register array concept for high-performance RISC processors," hicss, pp.181, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995
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