loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
28th Hawaii International Conference on System Sciences (HICSS'95)
Hawaii, USA
January 04-January 07
ISBN: 0-8186-6930-6
ASCII Text
x 
 
M. Natale, M. Baker, R. Collins, D. Wilson, S. Lucci, I. Gertner, "Pentium MPP for OLTP applications," Hawaii International Conference on System Sciences, pp. 95, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995.
 
 
BibTex
x
 
@article{ 10.1109/HICSS.1995.375405,
author = {M. Natale and M. Baker and R. Collins and D. Wilson and S. Lucci and I. Gertner},
title = {Pentium MPP for OLTP applications},
journal ={Hawaii International Conference on System Sciences},
volume = {0},
year = {1995},
issn = {1060-3425},
pages = {95},
doi = {http://doi.ieeecomputersociety.org/10.1109/HICSS.1995.375405},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Hawaii International Conference on System Sciences
TI - Pentium MPP for OLTP applications
SN - 1060-3425
SP
EP
A1 - M. Natale,
A1 - M. Baker,
A1 - R. Collins,
A1 - D. Wilson,
A1 - S. Lucci,
A1 - I. Gertner,
PY - 1995
KW - parallel architectures; shared memory systems; random-access storage; transaction processing; Pentium MPP; OLTP applications; multi-Pentium architecture; hierarchical memory; I/O bus subsystem; Pentium processors; RAM; hierarchical architecture; multiple boards; multiple cabinets; reflective memory; massively parallel processing
VL - 0
JA - Hawaii International Conference on System Sciences
ER -
 
M. Natale, Encore Comput. Corp., Fort Lauderdale, FL, USA
M. Baker, Encore Comput. Corp., Fort Lauderdale, FL, USA
R. Collins, Encore Comput. Corp., Fort Lauderdale, FL, USA
D. Wilson, Encore Comput. Corp., Fort Lauderdale, FL, USA
S. Lucci, Encore Comput. Corp., Fort Lauderdale, FL, USA
I. Gertner, Encore Comput. Corp., Fort Lauderdale, FL, USA
The paper describes a multi-Pentium architecture with a hierarchical memory and an I/O bus subsystem. On a board-level, this architecture achieves a very high-level of integration, by accommodating 8 Pentium processors with up to 2 Gigabytes of RAM. This hierarchical architecture has been extended to support multiple boards in a single cabinet as well as multiple cabinets connected via reflective memory.
Index Terms:
parallel architectures; shared memory systems; random-access storage; transaction processing; Pentium MPP; OLTP applications; multi-Pentium architecture; hierarchical memory; I/O bus subsystem; Pentium processors; RAM; hierarchical architecture; multiple boards; multiple cabinets; reflective memory; massively parallel processing
Citation:
M. Natale, M. Baker, R. Collins, D. Wilson, S. Lucci, I. Gertner, "Pentium MPP for OLTP applications," hicss, pp.95, 28th Hawaii International Conference on System Sciences (HICSS'95), 1995
Usage of this product signifies your acceptance of the Terms of Use.