This research presents for the first time an integer optimization approach for scheduling video computations on bus-constrained VLSI architectures or on an existing VLIW processor. For many video systems a combination of processor and VLSI chip provides a low cost solution that meets given performance requirements. Thus tools for analyzing whether a video function is best implemented in hardware (VLSI) or in software (on a VLIW processor) are valuable. An optimization approach is presented which can efficiently map video computations to hardware or software. The technique maps fast (I)DCT-II applications to an existing VLIW video signal processor chip. Our research shows that the optimized mapping to VLSI architectures provides up to 66% fewer busses than previous research. This research is important for industry since the partitioning of applications into software or hardware has a significant impact on the overall cost and performance of video processing systems.