7th IEEE International Symposium on High Assurance Systems Engineering (HASE'02)
Integration of Formal Specification into the Standard ASIC Design Flow
Tokyo, Japan
October 23-October 25
ISBN: 0-7695-1769-2
This paper presents our approach to leverage formal methods in an industrial design environment by closing the gap between the specification and design phases. We achieve this goal by deriving behavioural VHDL models from a formal system specification in tabular form that is easily accessible to mathematical analysis.
Citation:
Werner Haas, Stefan Gossens, Ulrich Heinkel, "Integration of Formal Specification into the Standard ASIC Design Flow," hase, pp.189, 7th IEEE International Symposium on High Assurance Systems Engineering (HASE'02), 2002