A Fully Pipelined, 700MBytes/s DES Encryption Core

G
GLSVLSI
1999
Ninth Great Lakes Symposium on VLSI
Abstract - A Fully Pipelined, 700MBytes/s DES Encryption Core

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Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	Ihn Kim, Craig S. Steele, Jefferey G. Koller, "A Fully Pipelined, 700MBytes/s DES Encryption Core," Great Lakes Symposium on VLSI, pp. 386, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757463, author = {Ihn Kim and Craig S. Steele and Jefferey G. Koller}, title = {A Fully Pipelined, 700MBytes/s DES Encryption Core}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {386}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757463}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - A Fully Pipelined, 700MBytes/s DES Encryption Core SN - 1066-1395 SP EP A1 - Ihn Kim, A1 - Craig S. Steele, A1 - Jefferey G. Koller, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Ihn Kim, University of Southern California

Craig S. Steele, University of Southern California

Jefferey G. Koller, University of Southern California

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757463

Fully-pipelined, 56-bit DES de/encryption and authentication at memory-bus bandwidths is now feasible. We describe a custom, 7 square mm, 120mW core in 4- metal 0.35mm CMOS. Performance allows on-the-fly encryption of 64-bit, 66MHz PCI traffic, and hence typical network traffic. FPGA, synthesized, and 3-metal versions are compared.

Citation:

Ihn Kim, Craig S. Steele, Jefferey G. Koller, "A Fully Pipelined, 700MBytes/s DES Encryption Core," glsvlsi, pp.386, Ninth Great Lakes Symposium on VLSI, 1999

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