Resonant Tunneling Transistors for Threshold Logic Circuit Applications

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	Similar Articles Articles by C. Pacha Articles by P. Glösekötter Articles by K. Goser Articles by U. Auer Articles by W. Prost Articles by F.-J. Tegude

Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	C. Pacha, P. Glösekötter, K. Goser, U. Auer, W. Prost, F.-J. Tegude, "Resonant Tunneling Transistors for Threshold Logic Circuit Applications," Great Lakes Symposium on VLSI, pp. 344, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757452, author = {C. Pacha and P. Glösekötter and K. Goser and U. Auer and W. Prost and F.-J. Tegude}, title = {Resonant Tunneling Transistors for Threshold Logic Circuit Applications}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {344}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757452}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Resonant Tunneling Transistors for Threshold Logic Circuit Applications SN - 1066-1395 SP EP A1 - C. Pacha, A1 - P. Glösekötter, A1 - K. Goser, A1 - U. Auer, A1 - W. Prost, A1 - F.-J. Tegude, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

C. Pacha, Universit?t Dortmund

P. Glösekötter, Universit?t Dortmund

K. Goser, Universit?t Dortmund

U. Auer, Universit?t Duisburg

W. Prost, Universit?t Duisburg

F.-J. Tegude, Universit?t Duisburg

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757452

Resonant tunneling transistors (RTT's) and linear threshold gates based on monostable-bistable logic transition elements (MOBILE's) are promising candidates for nano-scale integrated circuits. In this paper the design methodology of RTT logic gates is discussed and experimental results of a monolithically integrated NAND-NOR gate are presented. To exploit the computational functionality of threshold logic circuits a depth-2 full adder and a bit-level pipelined ripple carry adder are proposed.

Citation:

C. Pacha, P. Glösekötter, K. Goser, U. Auer, W. Prost, F.-J. Tegude, "Resonant Tunneling Transistors for Threshold Logic Circuit Applications," glsvlsi, pp.344, Ninth Great Lakes Symposium on VLSI, 1999

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