loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Ninth Great Lakes Symposium on VLSI
Assessing Defect Coverage of Memory Testing Algorithms
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
ASCII Text
x 
 
Vonkyoung Kim, Tom Chen, "Assessing Defect Coverage of Memory Testing Algorithms," Great Lakes Symposium on VLSI, pp. 340, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
x
 
@article{ 10.1109/GLSV.1999.757450,
author = {Vonkyoung Kim and Tom Chen},
title = {Assessing Defect Coverage of Memory Testing Algorithms},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {340},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757450},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Assessing Defect Coverage of Memory Testing Algorithms
SN - 1066-1395
SP
EP
A1 - Vonkyoung Kim,
A1 - Tom Chen,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Vonkyoung Kim, Sun Microsystems
Tom Chen, Colorado State University
This paper describes the defect coverage evaluation of memory testing algorithms. Realistic CMOS defects were extracted from a 2 ? 2 SRAM layout using an IFA tool, and circuit simulations were performed to measure the defect coverages of the eleven memory testing algorithms.
Citation:
Vonkyoung Kim, Tom Chen, "Assessing Defect Coverage of Memory Testing Algorithms," glsvlsi, pp.340, Ninth Great Lakes Symposium on VLSI, 1999
Usage of this product signifies your acceptance of the Terms of Use.