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Ninth Great Lakes Symposium on VLSI
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
ASCII Text
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S. Gailhard, N. Julien, A. Baganne, E. Martin, "Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures," Great Lakes Symposium on VLSI, pp. 334, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757447,
author = {S. Gailhard and N. Julien and A. Baganne and E. Martin},
title = {Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {334},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757447},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures
SN - 1066-1395
SP
EP
A1 - S. Gailhard,
A1 - N. Julien,
A1 - A. Baganne,
A1 - E. Martin,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
S. Gailhard, LESTER-UBS Lab
N. Julien, LESTER-UBS Lab
A. Baganne, LESTER-UBS Lab
E. Martin, LESTER-UBS Lab
The acoustic echo cancellation with adaptive filters is a computationally intensive problem that needs real time cost effective solutions for embedded systems. Low Power optimized signal processing architectures are likely to provide such solutions in the future. In this paper, we present different real-time optimized architectures of the popular Gmdf a algorithm, obtained by a HLS CAD tool providing trade-off between area and power dissipation.
Citation:
S. Gailhard, N. Julien, A. Baganne, E. Martin, "Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures," glsvlsi, pp.334, Ninth Great Lakes Symposium on VLSI, 1999
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