Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS

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Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	E. McShane, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, W.C. Fang, "Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS," Great Lakes Symposium on VLSI, pp. 332, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757446, author = {E. McShane and K. Shenai and L. Alkalai and E. Kolawa and V. Boyadzhyan and B. Blaes and W.C. Fang}, title = {Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {332}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757446}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS SN - 1066-1395 SP EP A1 - E. McShane, A1 - K. Shenai, A1 - L. Alkalai, A1 - E. Kolawa, A1 - V. Boyadzhyan, A1 - B. Blaes, A1 - W.C. Fang, PY - 1999 KW - Mixed-signal VLSI KW - low-power KW - microprocessor KW - RF KW - VLSI circuits process for mixed-signal VLSI in a die size measuring 2.2 mm x 2.2 mm. VL - 0 JA - Great Lakes Symposium on VLSI ER -

E. McShane, University of Illinois at Chicago

K. Shenai, University of Illinois at Chicago

L. Alkalai, California Institute of Technology

E. Kolawa, California Institute of Technology

V. Boyadzhyan, California Institute of Technology

B. Blaes, California Institute of Technology

W.C. Fang, California Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757446

A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver, and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital

Index Terms:

Mixed-signal VLSI, low-power, microprocessor, RF, VLSI circuits process for mixed-signal VLSI in a die size measuring 2.2 mm x 2.2 mm.

Citation:

E. McShane, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, W.C. Fang, "Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS," glsvlsi, pp.332, Ninth Great Lakes Symposium on VLSI, 1999

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