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Ninth Great Lakes Symposium on VLSI
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
ASCII Text
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Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman, "Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems," Great Lakes Symposium on VLSI, pp. 314, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757441,
author = {Radu M. Secareanu and Ivan S. Kourtev and Juan Becerra and Thomas E. Watrobski and Christopher Morton and William Staub and Thomas Tellier and Eby G. Friedman},
title = {Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {314},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757441},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems
SN - 1066-1395
SP
EP
A1 - Radu M. Secareanu,
A1 - Ivan S. Kourtev,
A1 - Juan Becerra,
A1 - Thomas E. Watrobski,
A1 - Christopher Morton,
A1 - William Staub,
A1 - Thomas Tellier,
A1 - Eby G. Friedman,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Radu M. Secareanu, University of Rochester
Ivan S. Kourtev, University of Rochester
Juan Becerra, University of Rochester
Thomas E. Watrobski, University of Rochester
Christopher Morton, University of Rochester
William Staub, University of Rochester
Thomas Tellier, University of Rochester
Eby G. Friedman, University of Rochester
Experimental data describing circuit and physical design issues that in uence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry affects digital latches. The experimental data characterize a variety of different noise mitigation techniques for the particular process technology, circuit structures, signal/clocking interdependencies, and related conditions.
Citation:
Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman, "Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems," glsvlsi, pp.314, Ninth Great Lakes Symposium on VLSI, 1999
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