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Ninth Great Lakes Symposium on VLSI
A Greedy Router with Technology Targetable Output
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
ASCII Text
x 
 
R. Balakrishnan, R.F. Hobson, "A Greedy Router with Technology Targetable Output," Great Lakes Symposium on VLSI, pp. 252, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757427,
author = {R. Balakrishnan and R.F. Hobson},
title = {A Greedy Router with Technology Targetable Output},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {252},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757427},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A Greedy Router with Technology Targetable Output
SN - 1066-1395
SP
EP
A1 - R. Balakrishnan,
A1 - R.F. Hobson,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
R. Balakrishnan, Simon Fraser University
R.F. Hobson, Simon Fraser University
Our objective was to integrate an effective channel routing algorithmwith the Chip Design Language (CDL) algorithmic layout tool. CDL uses technology targetable layout techniques, so that the output of the routing algorithm can easily be ported to different technologies. We introduce the technology independent features of CDL and describe how a greedy router can be interfaced to it. Specific features of interest include mapping from the grid based router to the gridless CDL environment, and the automatic insertion of CDL feed-through cells in multi-channel applications.
Citation:
R. Balakrishnan, R.F. Hobson, "A Greedy Router with Technology Targetable Output," glsvlsi, pp.252, Ninth Great Lakes Symposium on VLSI, 1999
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